1. Field of the Invention
The invention relates to a program-controlled method and apparatus for generating pulses of a predetermined time relation during successive intervals with a very high time resolution.
2. Background Art
Pulse trains of this kind are required for computer control means, such as those used to address main memories or buffers, and in particular for testing memory products (memories and associated buffers) of digital circuits, etc.
Memory products are tested by subjecting them to a predetermined pulse pattern. Their response to the pulse pattern applied is stored and compared with desired (theoretical) values. The result of the comparison indicates whether the memory product is operating as desired or whether errors have occurred at particular points.
The pulse train to be generated depends on the memory product specifications. On the basis of such (theoretical) values, the required pulse train is generated by a pulse generator.
Optimal testing should consider the fact that an event connected with the product to be tested may necessitate replacing a pulse train. This means that following such an event, the original pulse train may have to be replaced by another one.
Previously, the time resolution and accuracy of such pulse trains were limited by the circuits available for their generation and by technological and speed aspects.
FIG. 1A is a schematic simplified clock diagram of the state of the art test signal generation.
As shown in that figure, the test signals are generated by a test signal format-specific hardware circuit 1-1 from data and time generator signals. These test signals are applied to the product to be tested 1-2.
There may be various types of test signals. The product to be tested receives the test signals on different lines. For memory testing, the following test signal lines are provided, for example:
address lines;
write lines in response to which information is written into addressed memory positions;
read lines in response to which information is read from addressed memory positions;
data lines for carrying information (DATA IN) to be written into addressed memory positions;
data lines for carrying information (DATA OUT) to be read from addressed memory positions.
FIG. 1B is a schematic block diagram of a prior art test system, considering the generation of data and timing signals. This test system serves to generate test signal patterns. It comprises a time interval generator 1-3 which is connected to a processor 1-4. This processor supplies data for generating data signals in the signal processor 1-5, timing signals in the timer 1-6, and for program-controlling the format circuit 1-7 (see also FIG. 2). Signal processor 1-5 is preceded by a signal processor program memory SPPS 1-8 containing the operation codes for signal processor 1-5. Timer 1-6 is preceded by a timer memory 1-9 containing the time values for the timing signals during a particular time interval. The format circuit combines the data and the timing signals and assigns the test signal formats to the data signals. Embodiments of the timer 1-3 and the processor 1-4 are described in the U.S. Pat. No. 4,203,543 and in the U.S. Pat. No. 4,263,669. (The subject-matter of the latter patent constitutes an improvement over the former patent.) Details of the timer 1-6 are described in the U.S. Pat. No. 4,389,614 and in the U.S. Pat. No. 4,648,042. (The subject-matter of the latter patent constitutes an improvement over the former patent.)
According to the state of the art, the signal processor, if used only for address generation, may be a binary synchronous counter or, in the case of more complex data signals, an arithmetic logic circuit. In other words, to get from an address XX to an address YY, binary incrementation or decrementation or a logical address branch eliminating redundant count steps, may be used.
The essential disadvantage of prior art format circuits (1-7) is that their time inaccuracy is not correctable within tolerable limits. As the cycle times of the products to be tested become shorter, ever "faster" test systems are needed. However, even assuming "faster" components created as a result of such technical progress are used, the test systems available would still fall short of the required accuracy standards. Particular indispensable circuit-related components or component groups in known test systems have different signal paths and different delays leading to time inaccuracies. For example, internally used test systems of the applicant comprise flip-flop circuits with set, reset and clock inputs as well as XOR-circuits with, different signal delays between input and output.
This disadvantage may not be overcome either by interleaving or ordering two or several "slower" signal trains, as this would again necessitate using the previously mentioned XOR-circuits. The design of known interleave circuits is such that they only permit combining signals of uniform polarity in the real time mode. This leads to functional limitations in the interleave real time test mode.
Therefore, it is the object of the invention to provide test systems for ever "faster" products, such as memories and digital circuits, which are more accurate and universally applicable to test signal formats selectable in the interleave real time mode. Another object of the invention is to generate highly time-accurate digital control signals from data and timing signals, in particular for computer control means.